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Low-power high-efficiency video decoding using general purpose processors
Chi, Chi Ching; Álvarez-Mesa, Mauricio; Juurlink, Ben
In this article, we investigate how code optimization techniques and low-power states of general-purpose processors improve the power efficiency of HEVC decoding. The power and performance efficiency of the use of SIMD instructions, multicore architectures, and low-power active and idle states are analyzed in detail for offline video decoding. In addition, the power efficiency of techniques such as “race to idle” and “exploiting slack” with DVFS are evaluated for real-time video decoding. Results show that “exploiting slack” is more power efficient than “race to idle” for all evaluated platforms representing smartphone, tablet, laptop, and desktop computing systems.
Published in: ACM Transactions on Architecture and Code Optimization (TACO), 10.1145/2685551, Association for Computing Machinery (ACM)
