Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-9483
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Main Title: Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration
Author(s): Braun, Tanja
Becker, Karl-Friedrich
Hoelck, Ole
Voges, Steve
Kahle, Ruben
Dreissigacker, Marc
Schneider-Ramelow, Martin
Type: Article
Language Code: en
Abstract: Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.
URI: https://depositonce.tu-berlin.de/handle/11303/10554
http://dx.doi.org/10.14279/depositonce-9483
Issue Date: 23-May-2019
Date Available: 23-Dec-2019
DDC Class: 620 Ingenieurwissenschaften und zugeordnete Tätigkeiten
Subject(s): fan-out wafer level packaging
panel level packaging
heterogeneous integration
Sponsor/Funder: EC/H2020/644378/EU/Smart MEMs Piezo based energy Harvesting with Integrated Supercapacitor and packaging/smart-MEMPHIS
License: https://creativecommons.org/licenses/by/4.0/
Journal Title: Micromachines
Publisher: MDPI
Publisher Place: Basel
Volume: 10
Issue: 5
Article Number: 342
Publisher DOI: 10.3390/mi10050342
EISSN: 2072-666X
Appears in Collections:Forschungsschwerpunkt Technologien der Mikroperipherik » Publications

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