Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-14725
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dc.contributor.authorFekete, Sándor P.
dc.contributor.authorKöhler, Ekkehard
dc.contributor.authorTeich, Jürgen
dc.date.accessioned2021-12-17T10:17:28Z-
dc.date.available2021-12-17T10:17:28Z-
dc.date.issued2000
dc.identifier.issn2197-8085
dc.identifier.urihttps://depositonce.tu-berlin.de/handle/11303/15952-
dc.identifier.urihttp://dx.doi.org/10.14279/depositonce-14725-
dc.description.abstractWe consider the optimal placement of hardware modules in space and time for FPGA architectures with reconfiguration capabilities, where modules are three-dimensional boxes, with two dimensions corresponding to spatial cell requirements on the array and the third one describing execution time. Thus, optimal module placement can be modeled as a three-dimensional packing problem. A novel graph-theoretic characterization (by so-called "packing classes") of feasible packings and efficient families of lower bounds allow a drastic reduction of the search space, so that it is possible to solve the following problems for a given set of module tasks to optimality: (a) Find the minimal execution time of the given problem on an FPGA of fixed size, (b) Find the FPGA of minimal size to accomplish the tasks within a fixed time limit. Moreover, our approach allows the treatment of precedence constraints for the sequence of tasks, which are present in virtually all practical instances. These additional constraints cause serious problems to standard combinatorial algorithms. We show the packing class approach is perfectly suited for this type of problem. Additional mathematical structures are developed that lead to a powerful framework for computing optimal solutions. The usefulness is validated by computational results.en
dc.language.isoenen
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.ddc510 Mathematiken
dc.subject.otherfield-programmable gate arraysen
dc.subject.otherFPGA'sen
dc.subject.otherschedulingen
dc.subject.othermore-dimensional packingen
dc.subject.otherprecedence constraintsen
dc.subject.otherexact algorithmsen
dc.subject.otherinterval graphsen
dc.subject.otherpartial ordersen
dc.titleOptimal FPGA Module Placement with Temporal Precedence Constraintsen
dc.typeResearch Paperen
tub.accessrights.dnbfreeen
tub.publisher.universityorinstitutionTechnische Universität Berlinen
tub.series.issuenumber2000, 696en
tub.series.namePreprint-Reihe des Instituts für Mathematik, Technische Universität Berlinen
dc.type.versionsubmittedVersionen
tub.affiliationFak. 2 Mathematik und Naturwissenschaften » Inst. Mathematikde
tub.subject.msc200068M07 Mathematical problems of computer architectureen
tub.subject.msc200068R10 Graph theoryen
Appears in Collections:Technische Universität Berlin » Publications

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