Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-5736
Main Title: Implications of merging phases on scalability of multi-core architectures
Author(s): Manivannan, Madhavan
Juurlink, Ben
Stenstrom, Per
Type: Conference Object
Language Code: en
Abstract: Amdahl's Law dictates that in parallel applications serial sections establish an upper limit on the scalability. Asymmetric chip multiprocessors with a large core in addition to several small cores have been advocated for recently as a promising design paradigm because the large core can accelerate the execution of serial sections and hence mitigate the scalability bottlenecks due to large serial sections. This paper studies the scalability of a set of data mining workloads that have negligible serial sections. The formulation of Amdahl's Law, that optimistically assumes constant serial sections, estimates these workloads to scale to hundreds of cores in a chip multiprocessor (CMP). However the overhead in carrying out merging (or reduction) operations makes scalability to peak at lesser number. We establish this by extending theAmdahl's speedup model to factor in the impact of reduction operations on the speedup of applications on symmetric as well as asymmetric CMP designs. Our analytical model estimates that asymmetric CMPs with one large and many tiny cores are only optimal for applications with a low reduction overhead. However, as the overhead starts to increase, the balance is shifted towards using fewer but more capable cores. This eventually limits the performance advantage of asymmetric over symmetric CMPs.
URI: http://depositonce.tu-berlin.de/handle/11303/6171
http://dx.doi.org/10.14279/depositonce-5736
Issue Date: 2011
Date Available: 23-Feb-2017
DDC Class: 004 Datenverarbeitung; Informatik
620 Ingenieurwissenschaften und Maschinenbau
Subject(s): Amdahl's law
chip multiprocessor
redcution operations
Usage rights: Terms of German Copyright Law
Proceedings Title: 2011 International Conference on Parallel Processing : ICPP
Publisher: IEEE
Publisher Place: New York, NY [u.a.]
Publisher DOI: 10.1109/ICPP.2011.74
Page Start: 622
Page End: 631
ISBN: 978-1-4577-1336-1
ISSN: 0190-3918
Appears in Collections:Technische Universität Berlin » Fakultäten & Zentralinstitute » Fakultät 4 Elektrotechnik und Informatik » Institut für Technische Informatik und Mikroelektronik » Fachgebiet Architektur eingebetteter Systeme » Publications

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