Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-5743
Main Title: SynZEN: a hybrid TTA/VLIW architecture with a distributed register file
Author(s): Hauser, Stefan
Moser, Nico
Juurlink, Ben
Type: Conference Object
Language Code: en
Abstract: The quest for higher performance within a certain power budget in the fields of embedded computing demands unconventional architectural approaches. To this end, in this paper we present synZEN (sZ): a (micro-)architecture that combines features of very long instruction word (VLIW) and transport triggered architectures (TTAs) to cover the needs of different applications. SynZEN features a distributed register file (RF) (i.e., each functional unit (FU) has its own RF) and a wide memory connection to exploit spatial data locality. FPGA synthesis results demonstrate that due to the distributed RF the sZ design can be implemented in less area (in terms of FPGA slices) than existing TTA and VLIW designs. Furthermore, using two micro-benchmarks we show that because of the wide memory connection, sZ outperforms both the TTA as well as the VLIW design.
URI: http://depositonce.tu-berlin.de/handle/11303/6178
http://dx.doi.org/10.14279/depositonce-5743
Issue Date: 2012
Date Available: 23-Feb-2017
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): computer architecture
field programmable gate arrays
hardware
radio frequency
registers|VLIW
integrated circuit design
logic design
microprocessor chips
multiprocessing systems
Usage rights: Terms of German Copyright Law
Proceedings Title: NORCHIP 2012
Publisher: IEEE
Publisher Place: New York, NY [u.a.]
Publisher DOI: 10.1109/NORCHP.2012.6403142
Page Start: 1
Page End: 4
ISBN: 978-1-4673-2221-8
Appears in Collections:Technische Universität Berlin » Fakultäten & Zentralinstitute » Fakultät 4 Elektrotechnik und Informatik » Institut für Technische Informatik und Mikroelektronik » Fachgebiet Architektur eingebetteter Systeme » Publications

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