Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-5784
Main Title: How a single chip causes massive power bills
Subtitle: GPUSimPow: A GPGPU power simulator
Author(s): Lucas, Jan
Lal, Sohan
Andersch, Michael
Álvarez-Mesa, Mauricio
Juurlink, Ben
Type: Conference Object
Language Code: en
Abstract: Modern GPUs are true power houses in every meaning of the word: While they offer general-purpose (GPGPU) compute performance an order of magnitude higher than that of conventional CPUs, they have also been rapidly approaching the infamous “power wall”, as a single chip sometimes consumes more than 300W. Thus, the design space of GPGPU microarchitecture has been extended by another dimension: power. While GPU researchers have previously relied on cycle-accurate simulators for estimating performance during design cycles, there are no simulation tools that include power as well. To mitigate this issue, we introduce the GPUSimPow power estimation framework for GPGPUs consisting of both analytical and empirical models for regular and irregular hardware components. To validate this framework, we build a custom measurement setup to obtain power numbers from real graphics cards. An evaluation on a set of well-known benchmarks reveals an average relative error of 11.7% between simulated and hardware power for GT240 and an average relative error of 10.8% for GTX580. The simulator has been made available to the public [1].
URI: http://depositonce.tu-berlin.de/handle/11303/6225
http://dx.doi.org/10.14279/depositonce-5784
Issue Date: 2013
Date Available: 9-Mar-2017
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): general purpose computers
graphics processing units
memory architecture
computer architecture
hardware
kernel
power measurement
registers
Sponsor/Funder: EC/FP7/288653/EU/Low-Power Parallel Computing on GPUs/LPGPU
Usage rights: Terms of German Copyright Law
Proceedings Title: 2013 IEEE International Symposium on Performance Analysis of Systems and Software : ISPASS
Publisher: IEEE
Publisher Place: New York, NY [u.a.]
Publisher DOI: 10.1109/ISPASS.2013.6557150
Page Start: 97
Page End: 106
ISBN: 978-1-4673-5776-0
Appears in Collections:Technische Universität Berlin » Fakultäten & Zentralinstitute » Fakultät 4 Elektrotechnik und Informatik » Institut für Technische Informatik und Mikroelektronik » Fachgebiet Architektur eingebetteter Systeme » Publications

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