Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-5785
Main Title: High performance memory accesses on FPGA-SoCs
Subtitle: a quantitative analysis
Author(s): Göbel, Matthias
Chi, Chi Ching
Álvarez-Mesa, Mauricio
Juurlink, Ben
Type: Conference Object
Language Code: en
Abstract: FPGA-SoCs like Xilinx's Zynq-7000 and Altera's Generation 10 SoCs provide an integrated platform for HW/SW-co design applications. Computationally complex tasks can be implemented in the programmable logic part while control logic is implemented on the CPU. A potential bottleneck in such approaches is the interface latency and the data transfer throughput. Especially the data transfer to and from the memory subsystems can decrease the achievable performance significantly. Therefore, an analysis of the according subsystems of the Zynq-7000 has been performed in order to estimate the possible performance of HW/SW-codesigns with a special focus on two-dimensional memory accesses.
URI: http://depositonce.tu-berlin.de/handle/11303/6226
http://dx.doi.org/10.14279/depositonce-5785
Issue Date: 2015
Date Available: 9-Mar-2017
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): all programmable SoCs
FPGA-SoCs
HW/SW-codesign
memory access
Zynq-7000
interconnect network
video coding
Usage rights: Terms of German Copyright Law
Proceedings Title: 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines : FCCM
Publisher: IEEE
Publisher Place: New York, NY [u.a.]
Publisher DOI: 10.1109/FCCM.2015.23
Page Start: 32
Page End: 32
ISBN: 978-1-4799-9970-5
Appears in Collections:Technische Universität Berlin » Fakultäten & Zentralinstitute » Fakultät 4 Elektrotechnik und Informatik » Institut für Technische Informatik und Mikroelektronik » Fachgebiet Architektur eingebetteter Systeme » Publications

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