Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-6342
Main Title: A generic implementation of a quantified predictor on FPGAs
Author(s): Thomas, Gervin
Elhossini, Ahmed
Juurlink, Ben
Type: Conference Object
Language Code: en
Abstract: Predictors are used in many fields of computer architectures to enhance performance. With good estimations of future system behaviour, policies can be developed to improve system performance or reduce power consumption. These policies become more effective if the predictors are implemented in hardware and can provide quantified forecasts and not only binary ones. In this paper, we present and evaluate a generic predictor implemented in VHDL running on an FPGA which produces quantified forecasts. Moreover, a complete scalability analysis is presented which shows that our implementation has a maximum device utilization of less than 5%. Furthermore, we analyse the power consumption of the predictor running on an FPGA. Additionally, we show that this implementation can be clocked by over 210 MHz. Finally, we evaluate a power-saving policy based on our hardware predictor. Based on predicted idle periods, this power-saving policy uses power-saving modes and is able to reduce memory power consumption by 14.3%.
URI: https://depositonce.tu-berlin.de//handle/11303/7021
http://dx.doi.org/10.14279/depositonce-6342
Issue Date: 2014
Date Available: 26-Oct-2017
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): RTL
VHDL
power consumption
predictor
Usage rights: Terms of German Copyright Law
Proceedings Title: Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI
Publisher: Association for Computing Machinery (ACM)
Publisher Place: New York, NY
Publisher DOI: 10.1145/2591513.2591517
Page Start: 255
Page End: 260
ISBN: 978-1-4503-2816-6
Appears in Collections:Fachgebiet Architektur eingebetteter Systeme » Publications

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