Please use this identifier to cite or link to this item:
Main Title: Low-power high-efficiency video decoding using general purpose processors
Author(s): Chi, Chi Ching
Álvarez-Mesa, Mauricio
Juurlink, Ben
Type: Article
Language Code: en
Abstract: In this article, we investigate how code optimization techniques and low-power states of general-purpose processors improve the power efficiency of HEVC decoding. The power and performance efficiency of the use of SIMD instructions, multicore architectures, and low-power active and idle states are analyzed in detail for offline video decoding. In addition, the power efficiency of techniques such as “race to idle” and “exploiting slack” with DVFS are evaluated for real-time video decoding. Results show that “exploiting slack” is more power efficient than “race to idle” for all evaluated platforms representing smartphone, tablet, laptop, and desktop computing systems.
Issue Date: 2015
Date Available: 26-Oct-2017
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): Video decoding
low-power computing
parallel processing
Journal Title: ACM Transactions on Architecture and Code Optimization (TACO)
Publisher: Association for Computing Machinery (ACM)
Publisher Place: New York, NY
Volume: 11
Issue: 4
Article Number: 56
Publisher DOI: 10.1145/2685551
ISSN: 1544-3566
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

Files in This Item:
File Description SizeFormat 
Low_Power_High.pdf771.94 kBAdobe PDFThumbnail

Items in DepositOnce are protected by copyright, with all rights reserved, unless otherwise indicated.