Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-6778
Main Title: An efficient and flexible FPGA implementation of a face detection system
Author(s): Fekih, Hichem Ben
Elhossini, Ahmed
Juurlink, Ben
Type: Book Part
Language Code: en
Abstract: This paper proposes a hardware architecture based on the object detection system of Viola and Jones using Haar-like features. The proposed design is able to discover faces in real-time with high accuracy. Speed-up is achieved by exploiting the parallelism in the design, where multiple classifier cores can be added. To maintain a flexible design, classifier cores can be assigned to different images. Moreover using different training data, every core is able to detect a different object type. As development platform, the Zynq-7000 SoC from Xilinx is used, which features an ARM Cortex-A9 dual-core CPU and a programmable logic (FPGA). The current implementation focuses on the face detection and achieves a real-time detection at the rate of 16.53 FPS on image resolution of 640×480 pixels, which represents a speed-up of 6.46 times compared to the equivalent OpenCV software solution.
URI: https://depositonce.tu-berlin.de//handle/11303/7564
http://dx.doi.org/10.14279/depositonce-6778
Issue Date: 2015
Date Available: 12-Apr-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): face detection
computer vision
Zynq
FPGA
License: http://rightsstatements.org/vocab/InC/1.0/
Book Title: Applied Reconfigurable Computing. ARC 2015
Editor: Sano, Kentaro
Soudris, Dimitrios
Hübner, Michael
Diniz, Pedro C.
Publisher: Springer
Publisher Place: Berlin; Heidelberg
Volume: 2015
Publisher DOI: 10.1007/978-3-319-16214-0_20
Page Start: 243
Page End: 254
Series: Lecture Notes in Computer Science
Series Number: 9040
ISBN: 978-3-319-16214-0
ISSN: 1611-3349
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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