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Main Title: Design and Implementation of a High-Throughput CABAC Hardware Accelerator for the HEVC Decoder
Author(s): Habermann, Philipp
Type: Conference Object
Language Code: en
Abstract: HEVC is the new video coding standard of the Joint Collaborative Team on Video Coding. As in its predecessor H.264/AVC, Context-based Adaptive Binary Arithmetic Coding (CABAC) is a throughput bottleneck. This paper presents a hardware acceleration approach for transform coefficient decoding, the most time consuming part of CABAC in HEVC. In addition to a baseline design, a pipelined architecture and a parallel algorithm are implemented in an FPGA to evaluate the gain of these optimizations. The resulting baseline hardware design decodes 62 Mbins/s and achieves a 10× speed-up compared to an optimized software decoder for a typical workload at only a tenth of the processors clock frequency. The pipelined design gives an additional 13.5%, while the parallel design provides a 10% throughput improvement compared to the baseline. According to these results, HEVC CABAC decoding offers good hardware acceleration opportunities that should be further exploited in future work.
Issue Date: 2014
Date Available: 12-Apr-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): High Efficiency Video Coding
hardware acceleration
software decoder
hardware decoder
hybrid decoder
Proceedings Title: Informatiktage 2014 / Fachwissenschaftlicher Informatik-Kongress, 27. und 28. März 2014, Hasso-Plattner-Institut der Universität Potsdam
Publisher: Gesellschaft für Informatik
Publisher Place: Bonn
Volume: S-13
Page Start: 213
Page End: 216
Series: GI-Edition : lecture notes in informatics ; series of the Gesellschaft für Informatik
ISBN: 978-3-88579-447-9
ISSN: 1614-3213
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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