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Main Title: Optimal DC/AC Data Bus Inversion Coding
Author(s): Lucas, Jan
Lal, Sohan
Juurlink, Ben
Type: Conference Object
Language Code: en
Abstract: GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area.
Issue Date: 2018
Date Available: 1-Jun-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): data bus inversion
power consumption
termination power
Sponsor/Funder: EC/H2020/688759/EU/Low-Power Parallel Computing on GPUs 2/LPGPU2
Proceedings Title: Proceedings of the 2018 Design, Automation & Test in Europe (DATE) : 19-23 March 2018, Dresden, Germany
Publisher: EDAA
Publisher Place: [s.l.]
Publisher DOI: 10.23919/DATE.2018.8342169
Page Start: 1063
Page End: 1068
EISSN: 1558-1101
ISBN: 978-3-9819263-1-6
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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