Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-7065
Main Title: The SARC Architecture
Author(s): Ramirez, Alex
Cabarcas, Felipe
Juurlink, Ben
Álvarez-Mesa, Mauricio
Sanchez, Friman
Azevedo, Arnaldo
Meenderinck, Cor
Ciobanu, Cătălin
Isaza, Sebastian
Gaydadjiev, Georgi
Type: Article
Language Code: en
Abstract: The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.
URI: https://depositonce.tu-berlin.de//handle/11303/7904
http://dx.doi.org/10.14279/depositonce-7065
Issue Date: 2010
Date Available: 1-Jun-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): programming model
multicore
heterogeneous architecture
accelerator
License: http://rightsstatements.org/vocab/InC/1.0/
Journal Title: IEEE micro : chips, systems, software, and applications
Publisher: IEEE
Publisher Place: New York, NY [u.a.]
Volume: 30
Issue: 5
Publisher DOI: 10.1109/MM.2010.79
Page Start: 16
Page End: 29
EISSN: 1937-4143
ISSN: 0272-1732
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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