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Main Title: Efficient HEVC decoder for heterogeneous CPU with GPU systems
Author(s): Wang, Biao
Álvarez-Mesa, Mauricio
Chi, Chi Ching
Juurlink, Ben
de Souza, Diego F.
Ilic, Aleksandar
Roma, Nuno
Sousa, Leonel
Type: Conference Object
Language Code: en
Abstract: The High Efficiency Video Coding (HEVC) standard provides higher compression efficiency than other video coding standards but at the cost of increased computational load, which makes it hard to achieve real-time encoding/decoding of high-resolution, high-quality video sequences. In this paper, we investigate how Graphics Processing Units (GPUs) can be employed to accelerate HEVC decoding. GPUs are known to provide massive processing capability for throughput computing kernels, but the HEVC entropy decoding kernel cannot be executed efficiently on GPUs. We therefore propose a complete HEVC decoding solution for heterogeneous CPU+GPU systems, in which the entropy decoder is executed on the CPU and the remaining kernels on the GPU. Furthermore, the decoder is pipelined such that the CPU and the GPU can decode different frames in parallel. The proposed CPU+GPU decoder achieves an average frame rate of 150 frames per second for Ultra HD 4K video sequences when four CPU cores are used with an NVIDIA GeForce Titan X GPU.
Issue Date: 2016
Date Available: 7-Jun-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): decoding
Sponsor/Funder: EC/H2020/688759/EU/Low-Power Parallel Computing on GPUs 2/LPGPU2
Proceedings Title: 2016 IEEE 18th International Workshop on Multimedia Signal Processing (MMSP)
Publisher: IEEE
Publisher Place: Piscataway, NJ
Publisher DOI: 10.1109/MMSP.2016.7813353
Page Start: 1
Page End: 6
EISSN: 2473-3628
ISBN: 978-1-5090-3724-7
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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