Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-7085
Main Title: GPU Parallelization of HEVC In-Loop Filters
Author(s): Wang, Biao
de Souza, Diego F.
Álvarez-Mesa, Mauricio
Chi, Chi Ching
Juurlink, Ben
Ilic, Aleksandar
Roma, Nuno
Sousa, Leonel
Type: Article
Language Code: en
Abstract: In the High Efficiency Video Coding (HEVC) standard, multiple decoding modules have been designed to take advantage of parallel processing. In particular, the HEVC in-loop filters (i.e., the deblocking filter and sample adaptive offset) were conceived to be exploited by parallel architectures. However, the type of the offered parallelism mostly suits the capabilities of multi-core CPUs, thus making a real challenge to efficiently exploit massively parallel architectures such as Graphic Processing Units (GPUs), mainly due to the existing data dependencies between the HEVC decoding procedures. In accordance, this paper presents a novel strategy to increase the amount of parallelism and the resulting performance of the HEVC in-loop filters on GPU devices. For this purpose, the proposed algorithm performs the HEVC filtering at frame-level and employs intrinsic GPU vector instructions. When compared to the state-of-the-art HEVC in-loop filter implementations, the proposed approach also reduces the amount of required memory transfers, thus further boosting the performance. Experimental results show that the proposed GPU in-loop filters deliver a significant improvement in decoding performance. For example, average frame rates of 76 frames per second (FPS) and 125 FPS for Ultra HD 4K are achieved on an embedded NVIDIA GPU for All Intra and Random Access configurations, respectively.
URI: https://depositonce.tu-berlin.de//handle/11303/7924
http://dx.doi.org/10.14279/depositonce-7085
Issue Date: Jan-2017
Date Available: 8-Jun-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): HEVC
High Efficiency Video Coding
GPU
Graphics Processor Unit
in-loop filters
parallelization
decoder
video coding
License: http://rightsstatements.org/vocab/InC/1.0/
Journal Title: International journal of parallel programming
Publisher: Springer
Publisher Place: Dordrecht [u.a.]
Volume: 45
Issue: 6
Publisher DOI: 10.1007/s10766-017-0488-z
Page Start: 1515
Page End: 1535
EISSN: 1573-7640
ISSN: 0885-7458
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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