Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-7089
Main Title: A Quantitative Analysis of the Memory Architecture of FPGA-SoCs
Author(s): Göbel, Matthias
Elhossini, Ahmed
Chi, Chi Ching
Álvarez-Mesa, Mauricio
Juurlink, Ben
Type: Conference Object
Language Code: en
Abstract: In recent years, so called FPGA-SoCs have been introduced by Intel (formerly Altera) and Xilinx. These devices combine multi-core processors with programmable logic. This paper analyzes the various memory and communication interconnects found in actual devices, particularly the Zynq-7020 and Zynq-7045 from Xilinx and the Cyclone V SE SoC from Intel. Issues such as different access patterns, cache coherence and full-duplex communication are analyzed, for both generic accesses as well as for a real workload from the field of video coding. Furthermore, the paper shows that by carefully choosing the memory interconnect networks as well as the software interface, high-speed memory access can be achieved for various scenarios.
URI: https://depositonce.tu-berlin.de//handle/11303/7928
http://dx.doi.org/10.14279/depositonce-7089
Issue Date: 2017
Date Available: 8-Jun-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): programmable logic
memory
video coding
bandwidth
FPGA
License: http://rightsstatements.org/vocab/InC/1.0/
Proceedings Title: Applied reconfigurable computing : 13th International Symposium, ARC 2017, Delft, the Netherlands, April 3-7, 2017, Proceedings
Publisher: Springer
Publisher Place: Cham
Publisher DOI: 10.1007/978-3-319-56258-2_21
Page Start: 241
Page End: 252
Series: Lecture Notes in Computer Science
Series Number: 10216
EISSN: 1611-3349
ISBN: 978-3-319-56257-5
978-3-319-56258-2
ISSN: 0302-9743
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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