Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-7177
Main Title: Proximity Scheme for Instruction Caches in Tiled CMP Architectures
Author(s): Alawneh, Tareq
Chi, Chi Ching
Elhossini, Ahmed
Juurlink, Ben
Type: Article
Language Code: en
Abstract: Recent research results show that there is a high degree of code sharing between cores in multi-core architectures. In this paper we propose a proximity scheme for the instruction caches, a scheme in which the shared code blocks among the neighbouring L2 caches in tiled multi-core architectures are exploited to reduce the average cache miss penalty and the on-chip network traffic. We evaluate the proposed proximity scheme for instruction caches using a full-system simulator running an n-core tiled CMP. The experimental results reveal a significant execution time improvement of up to 91.4% for microbenchmarks whose instruction footprint does not fit in the private L2 cache. For real applications from the PARSEC benchmarks suite, the proposed scheme results in speedups of up to 8%.
URI: https://depositonce.tu-berlin.de//handle/11303/8014
http://dx.doi.org/10.14279/depositonce-7177
Issue Date: 2015
Date Available: 12-Jul-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): chip multiprocessor
multi-core architectures
cache
benchmark
CMP
License: http://rightsstatements.org/vocab/InC/1.0/
Journal Title: PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware
Publisher: Gesellschaft für Informatik e.V., Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware, PARS
Publisher Place: Erlangen
Volume: 32
Issue: 1
Page Start: 26
Page End: 37
ISSN: 0177-0454
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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