Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-7540
Main Title: Optimal DC/AC Data Bus Inversion Coding
Author(s): Lucas, Jan
Lal, Sohan
Juurlink, Ben
Type: Generic Research Data
Language Code: en
Abstract: GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area. This file provides the open research data for this paper.
URI: https://depositonce.tu-berlin.de//handle/11303/8391
http://dx.doi.org/10.14279/depositonce-7540
Issue Date: 29-Oct-2018
Date Available: 2-Nov-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): data bus inversion
DDR4
GDDR5
power consumption
termination power
Sponsor/Funder: EC/H2020/688759/EU/Low-Power Parallel Computing on GPUs 2/LPGPU2
License: http://rightsstatements.org/vocab/InC/1.0/
Is Supplement To: http://dx.doi.org/10.14279/depositonce-7061
Appears in Collections:FG Architektur eingebetteter Systeme » Research Data

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