Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-7559
Main Title: Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU
Author(s): Wang, Biao
de Souza, Diego F.
Álvarez-Mesa, Mauricio
Chi, Chi Ching
Juurlink, Ben
Ilic, Aleksandar
Roma, Nuno
Sousa, Leonel
Type: Article
Language Code: en
Abstract: The High Efficiency Video Coding HEVC standard provides a higher compression efficiency than other video coding standards but at the cost of an increased computational load, which makes hard to achieve real-time encoding/decoding for ultra high-resolution and high-quality video sequences. Graphics Processing Units GPU are known to provide massive processing capability for highly parallel and regular computing kernels, but not all HEVC decoding procedures are suited for GPU execution. Furthermore, if HEVC decoding is accelerated by GPUs, energy efficiency is another concern for heterogeneous CPU+GPU decoding. In this paper, a highly parallel HEVC decoder for heterogeneous CPU+GPU system is proposed. It exploits available parallelism in HEVC decoding on the CPU, GPU, and between the CPU and GPU devices simultaneously. On top of that, different workload balancing schemes can be selected according to the devoted CPU and GPU computing resources. Furthermore, an energy optimized solution is proposed by tuning GPU clock rates. Results show that the proposed decoder achieves better performance than the state-of-the-art CPU decoder, and the best performance among the workload balancing schemes depends on the available CPU and GPU computing resources. In particular, with an NVIDIA Titan X Maxwell GPU and an Intel Xeon E5-2699v3 CPU, the proposed decoder delivers 167 frames per second (fps) for Ultra HD 4K videos, when four CPU cores are used. Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of . When decoding performance is bounded by the CPU, a system wise energy reduction up to 36% is achieved by using fixed (and lower) GPU clocks, compared to the default dynamic clock settings on the GPU.
URI: https://depositonce.tu-berlin.de//handle/11303/8410
http://dx.doi.org/10.14279/depositonce-7559
Issue Date: 2017
Date Available: 6-Nov-2018
DDC Class: 004 Datenverarbeitung; Informatik
Subject(s): HEVC
High Efficiency Video Coding
CPU
GPU
video
decoding
Sponsor/Funder: EC/H2020/688759/EU/Low-Power Parallel Computing on GPUs 2/LPGPU2
License: https://creativecommons.org/licenses/by-nc-nd/4.0/
Journal Title: Signal processing: image communication
Publisher: Elsevier
Publisher Place: Amsterdam [u.a.]
Volume: 62
Publisher DOI: 10.1016/j.image.2017.12.009
Page Start: 93
Page End: 105
ISSN: 0923-5965
Is Version of: 10.1109/MMSP.2016.7813353
Appears in Collections:FG Architektur eingebetteter Systeme » Publications

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