Please use this identifier to cite or link to this item: http://dx.doi.org/10.14279/depositonce-8193
Main Title: Design and layout strategies for integrated frequency synthesizers with high spectral purity
Author(s): Herzel, Frank
Kissinger, Dietmar
Type: Article
Language Code: en
Abstract: Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.
URI: https://depositonce.tu-berlin.de//handle/11303/9092
http://dx.doi.org/10.14279/depositonce-8193
Issue Date: 2017
Date Available: 11-Feb-2019
DDC Class: 620 Ingenieurwissenschaften und zugeordnete Tätigkeiten
Subject(s): noise analysis
RF front-ends
frequency synthesizer
Sponsor/Funder: BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trägerfrequenz
License: http://rightsstatements.org/vocab/InC/1.0/
Journal Title: International Journal of Microwave and Wireless Technologies
Publisher: Cambridge University Press
Volume: 9
Issue: 9
Publisher DOI: 10.1017/S1759078717000654
Page Start: 1791
Page End: 1797
EISSN: 1759-0795
ISSN: 1759-0787
Notes: Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.
This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.
Appears in Collections:Inst. Hochfrequenz- und Halbleiter-Systemtechnologien » Publications

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