Optimal DC/AC Data Bus Inversion Coding
| dc.contributor.author | Lucas, Jan | |
| dc.contributor.author | Lal, Sohan | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2018-06-01T10:18:39Z | |
| dc.date.available | 2018-06-01T10:18:39Z | |
| dc.date.issued | 2018 | |
| dc.description.abstract | GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area. | en |
| dc.description.sponsorship | EC/H2020/688759/EU/Low-Power Parallel Computing on GPUs 2/LPGPU2 | en |
| dc.identifier.eissn | 1558-1101 | |
| dc.identifier.isbn | 978-3-9819263-1-6 | |
| dc.identifier.isbn | 978-3-9819263-0-9 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/7900 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-7061 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | data bus inversion | en |
| dc.subject.other | DDR4 | en |
| dc.subject.other | GDDR5 | en |
| dc.subject.other | power consumption | en |
| dc.subject.other | termination power | en |
| dc.title | Optimal DC/AC Data Bus Inversion Coding | en |
| dc.type | Conference Object | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.23919/DATE.2018.8342169 | en |
| dcterms.bibliographicCitation.originalpublishername | EDAA | en |
| dcterms.bibliographicCitation.originalpublisherplace | [s.l.] | en |
| dcterms.bibliographicCitation.pageend | 1068 | en |
| dcterms.bibliographicCitation.pagestart | 1063 | en |
| dcterms.bibliographicCitation.proceedingstitle | Proceedings of the 2018 Design, Automation & Test in Europe (DATE) : 19-23 March 2018, Dresden, Germany | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |