Real-Time Vision System for License Plate Detection and Recognition on FPGA
| dc.contributor.author | Rosli, Faird | |
| dc.contributor.author | Elhossini, Ahmed | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2018-07-13T09:22:52Z | |
| dc.date.available | 2018-07-13T09:22:52Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Rapid development of the Field Programmable Gate Array (FPGA) offers an alternative way to provide acceleration for computationally intensive tasks such as digital signal and image processing. Its ability to perform parallel processing shows the potential in implementing a high speed vision system. Out of numerous applications of computer vision, this paper focuses on the hardware implementation of one that is commercially known as Automatic Number Plate Recognition (ANPR).Morphological operations and Optical Character Recognition (OCR) algorithms have been implemented on a Xilinx Zynq-7000 All-Programmable SoC to realize the functions of an ANPR system. Test results have shown that the designed and implemented processing pipeline that consumed 63 % of the logic resources is capable of delivering the results with relatively low error rate. Most importantly, the computation time satisfies the real-time requirement for many ANPR applications. | en |
| dc.identifier.issn | 0177-0454 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/8019 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-7182 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | FPGA | en |
| dc.subject.other | Field Programmable Gate Array | en |
| dc.subject.other | ANPR | en |
| dc.subject.other | Automatic Number Plate Recognition | en |
| dc.subject.other | OCR | en |
| dc.subject.other | Optical Character Recognition | en |
| dc.subject.other | license plate detection | en |
| dc.title | Real-Time Vision System for License Plate Detection and Recognition on FPGA | en |
| dc.type | Article | en |
| dc.type.version | publishedVersion | en |
| dcterms.bibliographicCitation.issue | 1 | en |
| dcterms.bibliographicCitation.journaltitle | PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware | en |
| dcterms.bibliographicCitation.originalpublishername | Gesellschaft für Informatik e.V., Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware, PARS | en |
| dcterms.bibliographicCitation.originalpublisherplace | Erlangen | en |
| dcterms.bibliographicCitation.pageend | 79 | en |
| dcterms.bibliographicCitation.pagestart | 69 | en |
| dcterms.bibliographicCitation.volume | 32 | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |