Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine
| dc.contributor.author | Chi, Chi Ching | |
| dc.contributor.author | Juurlink, Ben | |
| dc.contributor.author | Meenderinck, Cor | |
| dc.date.accessioned | 2017-10-24T10:05:20Z | |
| dc.date.available | 2017-10-24T10:05:20Z | |
| dc.date.issued | 2010 | |
| dc.description.abstract | How to develop efficient and scalable parallel applications is the key challenge for emerging many-core architectures. We investigate this question by implementing and comparing two parallel H.264 decoders on the Cell architecture. It is expected that future many-cores will use a Cell-like local store memory hierarchy, rather than a non-scalable shared memory. The two implemented parallel algorithms, the Task Pool (TP) and the novel Ring-Line (RL) approach, both exploit macroblock-level parallelism. The TP implementation follows the master-slave paradigm and is very dynamic so that in theory perfect load balancing can be achieved. The RL approach is distributed and more predictable in the sense that the mapping of macroblocks to processing elements is fixed. This allows to better exploit data locality, to overlap communication with computation, and to reduce communication and synchronization overhead. While TP is more scalable in theory, the actual scalability favors RL. Using 16 SPEs, RL obtains a scalability of 12x, while TP achieves only 10.3x. More importantly, the absolute performance of RL is much higher. Using 16 SPEs, RL achieves a throughput of 139.6 frames per second (fps) while TP achieves only 76.6 fps. A large part of the additional performance advantage is due to hiding the memory latency. From the results we conclude that in order to fully leverage the performance of future many-cores, a centralized master should be avoided and the mapping of tasks to cores should be predictable in order to be able to hide the memory latency. | en |
| dc.identifier.isbn | 978-1-4503-0018-6 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/6924 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-6263 | |
| dc.language.iso | en | |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | |
| dc.subject.other | H.264 | en |
| dc.subject.other | cell | en |
| dc.subject.other | decoding | en |
| dc.subject.other | parallel | en |
| dc.subject.other | programming | en |
| dc.subject.other | video | en |
| dc.title | Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine | en |
| dc.type | Conference Object | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1145/1810085.1810102 | |
| dcterms.bibliographicCitation.originalpublishername | Association for Computing Machinery (ACM) | en |
| dcterms.bibliographicCitation.originalpublisherplace | New York, NY | en |
| dcterms.bibliographicCitation.pageend | 114 | |
| dcterms.bibliographicCitation.pagestart | 105 | |
| dcterms.bibliographicCitation.proceedingstitle | Proceedings of the 24th ACM International Conference on Supercomputing | en |
| tub.accessrights.dnb | domain | |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |
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