A Benchmark Suite for Evaluating Parallel Programming Models

dc.contributor.authorAndersch, Michael
dc.contributor.authorJuurlink, Ben
dc.contributor.authorChi, Chi Ching
dc.date.accessioned2018-07-11T08:40:54Z
dc.date.available2018-07-11T08:40:54Z
dc.date.issued2011
dc.description.abstractThe transition to multi-core processors enforces software developers to explicitly exploit thread-level parallelism to increase performance. The associated programmability problem has led to the introduction of a plethora of parallel programming models that aim at simplifying software development by raising the abstraction level. Since industry has not settled for a single model, however, multiple significantly different approaches exist. This work presents a benchmark suite which can be used to classify and compare such parallel programming models and, therefore, aids in selecting the appropriate programming model for a given task. After a detailed explanation of the suite's design, preliminary results for two programming models, Pthreads and OmpSs/SMPSs, are presented and analyzed, leading to an outline of further extensions of the suite.en
dc.description.sponsorshipEC/FP7/248647/EU/ENabling technologies for a programmable many-CORE/ENCOREen
dc.identifier.issn0177-0454
dc.identifier.urihttps://depositonce.tu-berlin.de//handle/11303/8009
dc.identifier.urihttp://dx.doi.org/10.14279/depositonce-7172
dc.identifier.urihttps://hdl.handle.net/20.500.12116/8577
dc.language.isoenen
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.ddc004 Datenverarbeitung; Informatikde
dc.subject.otherprogramming modelen
dc.subject.otherbenchmark suiteen
dc.subject.otherparallelization approachen
dc.subject.otherparallel programming modelen
dc.subject.otherchip multiprocessoren
dc.titleA Benchmark Suite for Evaluating Parallel Programming Modelsen
dc.title.subtitleIntroduction and Preliminary Resultsen
dc.typeArticleen
dc.type.versionpublishedVersionen
dcterms.bibliographicCitation.issue1en
dcterms.bibliographicCitation.journaltitlePARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftwareen
dcterms.bibliographicCitation.originalpublishernameGesellschaft für Informatik e.V., Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware, PARSen
dcterms.bibliographicCitation.originalpublisherplaceErlangenen
dcterms.bibliographicCitation.pageend17en
dcterms.bibliographicCitation.pagestart7en
dcterms.bibliographicCitation.volume28en
tub.accessrights.dnbfreeen
tub.affiliationFak. 4 Elektrotechnik und Informatik>Inst. Technische Informatik und Mikroelektronik>FG Architektur eingebetteter Systemede
tub.affiliation.facultyFak. 4 Elektrotechnik und Informatikde
tub.affiliation.groupFG Architektur eingebetteter Systemede
tub.affiliation.instituteInst. Technische Informatik und Mikroelektronikde
tub.publisher.universityorinstitutionTechnische Universität Berlinen
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