Automatic Data Layout Optimizations for GPUs
| dc.contributor.author | Kofler, Klaus | |
| dc.contributor.author | Cosenza, Biagio | |
| dc.contributor.author | Fahringer, Thomas | |
| dc.date.accessioned | 2018-06-04T14:59:51Z | |
| dc.date.available | 2018-06-04T14:59:51Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Memory optimizations have became increasingly important in order to fully exploit the computational power of modern GPUs. The data arrangement has a big impact on the performance, and it is very hard for GPU programmers to identify a well-suited data layout. Classical data layout transformations include grouping together data fields that have similar access patterns, or transforming Array-of-Structures (AoS) to Structure-of-Arrays (SoA). This paper presents an optimization infrastructure to automatically determine an improved data layout for OpenCL programs written in AoS layout. Our framework consists of two separate algorithms: The first one constructs a graph-based model, which is used to split the AoS input struct into several clusters of fields, based on hardware dependent parameters. The second algorithm selects a good per-cluster data layout (e.g., SoA, AoS or an intermediate layout) using a decision tree. Results show that the combination of both algorithms is able to deliver higher performance than the individual algorithms. The layouts proposed by our framework result in speedups of up to 2.22, 1.89 and 2.83 on an AMD FirePro S9000, NVIDIA GeForce GTX 480 and NVIDIA Tesla k20m, respectively, over different AoS sample programs, and up to 1.18 over a manually optimized program. | en |
| dc.identifier.isbn | 978-3-662-48096-0 | |
| dc.identifier.isbn | 978-3-662-48095-3 | |
| dc.identifier.issn | 0302-9743 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/7910 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-7071 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | GPU | en |
| dc.subject.other | OpenCL | en |
| dc.subject.other | Array-of-Structures | en |
| dc.subject.other | Structure-of-Arrays | en |
| dc.subject.other | AoS | en |
| dc.subject.other | SoA | en |
| dc.subject.other | memory | en |
| dc.subject.other | data layout | en |
| dc.subject.other | graph-based model | en |
| dc.title | Automatic Data Layout Optimizations for GPUs | en |
| dc.type | Conference Object | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1007/978-3-662-48096-0_21 | en |
| dcterms.bibliographicCitation.originalpublishername | Springer | en |
| dcterms.bibliographicCitation.originalpublisherplace | Berlin ; Heidelberg ; New York, NY | en |
| dcterms.bibliographicCitation.pageend | 274 | en |
| dcterms.bibliographicCitation.pagestart | 263 | en |
| dcterms.bibliographicCitation.proceedingstitle | Euro-Par 2015: Parallel Processing. Euro-Par 2015. (Lecture Notes in Computer Science, vol 9233) | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |