The SARC Architecture
| dc.contributor.author | Ramirez, Alex | |
| dc.contributor.author | Cabarcas, Felipe | |
| dc.contributor.author | Juurlink, Ben | |
| dc.contributor.author | Álvarez-Mesa, Mauricio | |
| dc.contributor.author | Sanchez, Friman | |
| dc.contributor.author | Azevedo, Arnaldo | |
| dc.contributor.author | Meenderinck, Cor | |
| dc.contributor.author | Ciobanu, Cătălin | |
| dc.contributor.author | Isaza, Sebastian | |
| dc.contributor.author | Gaydadjiev, Georgi | |
| dc.date.accessioned | 2018-06-01T11:35:35Z | |
| dc.date.available | 2018-06-01T11:35:35Z | |
| dc.date.issued | 2010 | |
| dc.description.abstract | The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors. | en |
| dc.identifier.eissn | 1937-4143 | |
| dc.identifier.issn | 0272-1732 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/7904 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-7065 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | programming model | en |
| dc.subject.other | multicore | en |
| dc.subject.other | heterogeneous architecture | en |
| dc.subject.other | accelerator | en |
| dc.title | The SARC Architecture | en |
| dc.type | Article | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1109/MM.2010.79 | en |
| dcterms.bibliographicCitation.issue | 5 | en |
| dcterms.bibliographicCitation.journaltitle | IEEE micro : chips, systems, software, and applications | en |
| dcterms.bibliographicCitation.originalpublishername | IEEE | en |
| dcterms.bibliographicCitation.originalpublisherplace | New York, NY [u.a.] | en |
| dcterms.bibliographicCitation.pageend | 29 | en |
| dcterms.bibliographicCitation.pagestart | 16 | en |
| dcterms.bibliographicCitation.volume | 30 | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |