The SARC Architecture

dc.contributor.authorRamirez, Alex
dc.contributor.authorCabarcas, Felipe
dc.contributor.authorJuurlink, Ben
dc.contributor.authorÁlvarez-Mesa, Mauricio
dc.contributor.authorSanchez, Friman
dc.contributor.authorAzevedo, Arnaldo
dc.contributor.authorMeenderinck, Cor
dc.contributor.authorCiobanu, Cătălin
dc.contributor.authorIsaza, Sebastian
dc.contributor.authorGaydadjiev, Georgi
dc.date.accessioned2018-06-01T11:35:35Z
dc.date.available2018-06-01T11:35:35Z
dc.date.issued2010
dc.description.abstractThe SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.en
dc.identifier.eissn1937-4143
dc.identifier.issn0272-1732
dc.identifier.urihttps://depositonce.tu-berlin.de//handle/11303/7904
dc.identifier.urihttp://dx.doi.org/10.14279/depositonce-7065
dc.language.isoenen
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.ddc004 Datenverarbeitung; Informatikde
dc.subject.otherprogramming modelen
dc.subject.othermulticoreen
dc.subject.otherheterogeneous architectureen
dc.subject.otheracceleratoren
dc.titleThe SARC Architectureen
dc.typeArticleen
dc.type.versionacceptedVersionen
dcterms.bibliographicCitation.doi10.1109/MM.2010.79en
dcterms.bibliographicCitation.issue5en
dcterms.bibliographicCitation.journaltitleIEEE micro : chips, systems, software, and applicationsen
dcterms.bibliographicCitation.originalpublishernameIEEEen
dcterms.bibliographicCitation.originalpublisherplaceNew York, NY [u.a.]en
dcterms.bibliographicCitation.pageend29en
dcterms.bibliographicCitation.pagestart16en
dcterms.bibliographicCitation.volume30en
tub.accessrights.dnbfreeen
tub.affiliationFak. 4 Elektrotechnik und Informatik>Inst. Technische Informatik und Mikroelektronik>FG Architektur eingebetteter Systemede
tub.affiliation.facultyFak. 4 Elektrotechnik und Informatikde
tub.affiliation.groupFG Architektur eingebetteter Systemede
tub.affiliation.instituteInst. Technische Informatik und Mikroelektronikde
tub.publisher.universityorinstitutionTechnische Universität Berlinen
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