Proximity Scheme for Instruction Caches in Tiled CMP Architectures
| dc.contributor.author | Alawneh, Tareq | |
| dc.contributor.author | Chi, Chi Ching | |
| dc.contributor.author | Elhossini, Ahmed | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2018-07-12T12:06:53Z | |
| dc.date.available | 2018-07-12T12:06:53Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Recent research results show that there is a high degree of code sharing between cores in multi-core architectures. In this paper we propose a proximity scheme for the instruction caches, a scheme in which the shared code blocks among the neighbouring L2 caches in tiled multi-core architectures are exploited to reduce the average cache miss penalty and the on-chip network traffic. We evaluate the proposed proximity scheme for instruction caches using a full-system simulator running an n-core tiled CMP. The experimental results reveal a significant execution time improvement of up to 91.4% for microbenchmarks whose instruction footprint does not fit in the private L2 cache. For real applications from the PARSEC benchmarks suite, the proposed scheme results in speedups of up to 8%. | en |
| dc.identifier.issn | 0177-0454 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/8014 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-7177 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | chip multiprocessor | en |
| dc.subject.other | multi-core architectures | en |
| dc.subject.other | cache | en |
| dc.subject.other | benchmark | en |
| dc.subject.other | CMP | en |
| dc.title | Proximity Scheme for Instruction Caches in Tiled CMP Architectures | en |
| dc.type | Article | en |
| dc.type.version | publishedVersion | en |
| dcterms.bibliographicCitation.issue | 1 | en |
| dcterms.bibliographicCitation.journaltitle | PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware | en |
| dcterms.bibliographicCitation.originalpublishername | Gesellschaft für Informatik e.V., Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware, PARS | en |
| dcterms.bibliographicCitation.originalpublisherplace | Erlangen | en |
| dcterms.bibliographicCitation.pageend | 37 | en |
| dcterms.bibliographicCitation.pagestart | 26 | en |
| dcterms.bibliographicCitation.volume | 32 | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |