SynZEN: a hybrid TTA/VLIW architecture with a distributed register file
| dc.contributor.author | Hauser, Stefan | |
| dc.contributor.author | Moser, Nico | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2017-02-23T09:48:44Z | |
| dc.date.available | 2017-02-23T09:48:44Z | |
| dc.date.issued | 2012 | |
| dc.description.abstract | The quest for higher performance within a certain power budget in the fields of embedded computing demands unconventional architectural approaches. To this end, in this paper we present synZEN (sZ): a (micro-)architecture that combines features of very long instruction word (VLIW) and transport triggered architectures (TTAs) to cover the needs of different applications. SynZEN features a distributed register file (RF) (i.e., each functional unit (FU) has its own RF) and a wide memory connection to exploit spatial data locality. FPGA synthesis results demonstrate that due to the distributed RF the sZ design can be implemented in less area (in terms of FPGA slices) than existing TTA and VLIW designs. Furthermore, using two micro-benchmarks we show that because of the wide memory connection, sZ outperforms both the TTA as well as the VLIW design. | en |
| dc.identifier.isbn | 978-1-4673-2221-8 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/6178 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-5743 | |
| dc.language.iso | en | |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | |
| dc.subject.other | computer architecture | en |
| dc.subject.other | field programmable gate arrays | en |
| dc.subject.other | hardware | en |
| dc.subject.other | radio frequency | en |
| dc.subject.other | registers|VLIW | en |
| dc.subject.other | integrated circuit design | en |
| dc.subject.other | logic design | en |
| dc.subject.other | microprocessor chips | en |
| dc.subject.other | multiprocessing systems | en |
| dc.title | SynZEN: a hybrid TTA/VLIW architecture with a distributed register file | en |
| dc.type | Conference Object | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1109/NORCHP.2012.6403142 | |
| dcterms.bibliographicCitation.originalpublishername | IEEE | en |
| dcterms.bibliographicCitation.originalpublisherplace | New York, NY [u.a.] | en |
| dcterms.bibliographicCitation.pageend | 4 | |
| dcterms.bibliographicCitation.pagestart | 1 | |
| dcterms.bibliographicCitation.proceedingstitle | NORCHIP 2012 | en |
| tub.accessrights.dnb | domain | |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |
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