Parallel HEVC Decoding on Multi- and Many-core Architectures
| dc.contributor.author | Chi, Chi Ching | |
| dc.contributor.author | Álvarez-Mesa, Mauricio | |
| dc.contributor.author | Lucas, Jan | |
| dc.contributor.author | Juurlink, Ben | |
| dc.contributor.author | Schierl, Thomas | |
| dc.date.accessioned | 2018-04-12T16:18:44Z | |
| dc.date.available | 2018-04-12T16:18:44Z | |
| dc.date.issued | 2013 | |
| dc.description.abstract | The Joint Collaborative Team on Video Decoding is developing a new standard named High Efficiency Video Coding (HEVC) that aims at reducing the bitrate of H.264/AVC by another 50 %. In order to fulfill the computational demands of the new standard, in particular for high resolutions and at low power budgets, exploiting parallelism is no longer an option but a requirement. Therefore, HEVC includes several coding tools that allows to divide each picture into several partitions that can be processed in parallel, without degrading the quality nor the bitrate. In this paper we adapt one of these approaches, the Wavefront Parallel Processing (WPP) coding, and show how it can be implemented on multi- and many-core processors. Our approach, named Overlapped Wavefront (OWF), processes several partitions as well as several pictures in parallel. This has the advantage that the amount of (thread-level) parallelism stays constant during execution. In addition, performance and power results are provided for three platforms: a server Intel CPU with 8 cores, a laptop Intel CPU with 4 cores, and a TILE-Gx36 with 36 cores from Tilera. The results show that our parallel HEVC decoder is capable of achieving an average frame rate of 116 fps for 4k resolution on a standard multicore CPU. The results also demonstrate that exploiting more parallelism by increasing the number of cores can improve the energy efficiency measured in terms of Joules per frame substantially. | en |
| dc.identifier.eissn | 1939-8115 | |
| dc.identifier.issn | 1939-8018 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/7571 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-6785 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | HEVC | en |
| dc.subject.other | video coding | en |
| dc.subject.other | parallel processing | en |
| dc.subject.other | power analysis | en |
| dc.subject.other | real-time 4k | en |
| dc.subject.other | UHD | en |
| dc.title | Parallel HEVC Decoding on Multi- and Many-core Architectures | en |
| dc.title.subtitle | A Power and Performance Analysis | en |
| dc.type | Article | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1007/s11265-012-0714-2 | en |
| dcterms.bibliographicCitation.issue | 3 | en |
| dcterms.bibliographicCitation.journaltitle | Journal of signal processing systems | en |
| dcterms.bibliographicCitation.originalpublishername | Springer | en |
| dcterms.bibliographicCitation.originalpublisherplace | Norwell, Mass. | en |
| dcterms.bibliographicCitation.pageend | 260 | en |
| dcterms.bibliographicCitation.pagestart | 247 | en |
| dcterms.bibliographicCitation.volume | 71 | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |