Parallel HEVC Decoding on Multi- and Many-core Architectures

dc.contributor.authorChi, Chi Ching
dc.contributor.authorÁlvarez-Mesa, Mauricio
dc.contributor.authorLucas, Jan
dc.contributor.authorJuurlink, Ben
dc.contributor.authorSchierl, Thomas
dc.date.accessioned2018-04-12T16:18:44Z
dc.date.available2018-04-12T16:18:44Z
dc.date.issued2013
dc.description.abstractThe Joint Collaborative Team on Video Decoding is developing a new standard named High Efficiency Video Coding (HEVC) that aims at reducing the bitrate of H.264/AVC by another 50 %. In order to fulfill the computational demands of the new standard, in particular for high resolutions and at low power budgets, exploiting parallelism is no longer an option but a requirement. Therefore, HEVC includes several coding tools that allows to divide each picture into several partitions that can be processed in parallel, without degrading the quality nor the bitrate. In this paper we adapt one of these approaches, the Wavefront Parallel Processing (WPP) coding, and show how it can be implemented on multi- and many-core processors. Our approach, named Overlapped Wavefront (OWF), processes several partitions as well as several pictures in parallel. This has the advantage that the amount of (thread-level) parallelism stays constant during execution. In addition, performance and power results are provided for three platforms: a server Intel CPU with 8 cores, a laptop Intel CPU with 4 cores, and a TILE-Gx36 with 36 cores from Tilera. The results show that our parallel HEVC decoder is capable of achieving an average frame rate of 116 fps for 4k resolution on a standard multicore CPU. The results also demonstrate that exploiting more parallelism by increasing the number of cores can improve the energy efficiency measured in terms of Joules per frame substantially.en
dc.identifier.eissn1939-8115
dc.identifier.issn1939-8018
dc.identifier.urihttps://depositonce.tu-berlin.de//handle/11303/7571
dc.identifier.urihttp://dx.doi.org/10.14279/depositonce-6785
dc.language.isoenen
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.ddc004 Datenverarbeitung; Informatikde
dc.subject.otherHEVCen
dc.subject.othervideo codingen
dc.subject.otherparallel processingen
dc.subject.otherpower analysisen
dc.subject.otherreal-time 4ken
dc.subject.otherUHDen
dc.titleParallel HEVC Decoding on Multi- and Many-core Architecturesen
dc.title.subtitleA Power and Performance Analysisen
dc.typeArticleen
dc.type.versionacceptedVersionen
dcterms.bibliographicCitation.doi10.1007/s11265-012-0714-2en
dcterms.bibliographicCitation.issue3en
dcterms.bibliographicCitation.journaltitleJournal of signal processing systemsen
dcterms.bibliographicCitation.originalpublishernameSpringeren
dcterms.bibliographicCitation.originalpublisherplaceNorwell, Mass.en
dcterms.bibliographicCitation.pageend260en
dcterms.bibliographicCitation.pagestart247en
dcterms.bibliographicCitation.volume71en
tub.accessrights.dnbfreeen
tub.affiliationFak. 4 Elektrotechnik und Informatik>Inst. Technische Informatik und Mikroelektronik>FG Architektur eingebetteter Systemede
tub.affiliation.facultyFak. 4 Elektrotechnik und Informatikde
tub.affiliation.groupFG Architektur eingebetteter Systemede
tub.affiliation.instituteInst. Technische Informatik und Mikroelektronikde
tub.publisher.universityorinstitutionTechnische Universität Berlinen
Files
Original bundle
Now showing 1 - 1 of 1
Loading…
Thumbnail Image
Name:
10.1007.s11265-012-0714-2.pdf
Size:
2.11 MB
Format:
Adobe Portable Document Format
Description:
Collections