Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU

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dc.contributor.authorWang, Biao
dc.contributor.authorde Souza, Diego F.
dc.contributor.authorÁlvarez-Mesa, Mauricio
dc.contributor.authorChi, Chi Ching
dc.contributor.authorJuurlink, Ben
dc.contributor.authorIlic, Aleksandar
dc.contributor.authorRoma, Nuno
dc.contributor.authorSousa, Leonel
dc.date.accessioned2018-11-06T16:14:30Z
dc.date.available2018-11-06T16:14:30Z
dc.date.issued2017
dc.description.abstractThe High Efficiency Video Coding HEVC standard provides a higher compression efficiency than other video coding standards but at the cost of an increased computational load, which makes hard to achieve real-time encoding/decoding for ultra high-resolution and high-quality video sequences. Graphics Processing Units GPU are known to provide massive processing capability for highly parallel and regular computing kernels, but not all HEVC decoding procedures are suited for GPU execution. Furthermore, if HEVC decoding is accelerated by GPUs, energy efficiency is another concern for heterogeneous CPU+GPU decoding. In this paper, a highly parallel HEVC decoder for heterogeneous CPU+GPU system is proposed. It exploits available parallelism in HEVC decoding on the CPU, GPU, and between the CPU and GPU devices simultaneously. On top of that, different workload balancing schemes can be selected according to the devoted CPU and GPU computing resources. Furthermore, an energy optimized solution is proposed by tuning GPU clock rates. Results show that the proposed decoder achieves better performance than the state-of-the-art CPU decoder, and the best performance among the workload balancing schemes depends on the available CPU and GPU computing resources. In particular, with an NVIDIA Titan X Maxwell GPU and an Intel Xeon E5-2699v3 CPU, the proposed decoder delivers 167 frames per second (fps) for Ultra HD 4K videos, when four CPU cores are used. Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of . When decoding performance is bounded by the CPU, a system wise energy reduction up to 36% is achieved by using fixed (and lower) GPU clocks, compared to the default dynamic clock settings on the GPU.en
dc.description.sponsorshipEC/H2020/688759/EU/Low-Power Parallel Computing on GPUs 2/LPGPU2en
dc.identifier.issn0923-5965
dc.identifier.urihttps://depositonce.tu-berlin.de/handle/11303/8410
dc.identifier.urihttp://dx.doi.org/10.14279/depositonce-7559
dc.language.isoenen
dc.relation.isversionof10.1109/MMSP.2016.7813353
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/4.0/en
dc.subject.ddc004 Datenverarbeitung; Informatiken
dc.subject.otherHEVCen
dc.subject.otherHigh Efficiency Video Codingen
dc.subject.otherCPUen
dc.subject.otherGPUen
dc.subject.othervideoen
dc.subject.otherdecodingen
dc.titleHighly parallel HEVC decoding for heterogeneous systems with CPU and GPUen
dc.typeArticleen
dc.type.versionacceptedVersionen
dcterms.bibliographicCitation.doi10.1016/j.image.2017.12.009en
dcterms.bibliographicCitation.journaltitleSignal processing: image communicationen
dcterms.bibliographicCitation.originalpublishernameElsevieren
dcterms.bibliographicCitation.originalpublisherplaceAmsterdam [u.a.]en
dcterms.bibliographicCitation.pageend105en
dcterms.bibliographicCitation.pagestart93en
dcterms.bibliographicCitation.volume62en
tub.accessrights.dnbfreeen
tub.affiliationFak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systemede
tub.affiliation.facultyFak. 4 Elektrotechnik und Informatikde
tub.affiliation.groupFG Architektur eingebetteter Systemede
tub.affiliation.instituteInst. Technische Informatik und Mikroelektronikde
tub.publisher.universityorinstitutionTechnische Universität Berlinen

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