A QHD-capable parallel H.264 decoder
| dc.contributor.author | Chi, Chi Ching | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2017-10-26T10:38:31Z | |
| dc.date.available | 2017-10-26T10:38:31Z | |
| dc.date.issued | 2011 | |
| dc.description.abstract | Video coding follows the trend of demanding higher performance every new generation, and therefore could utilize many-cores. A complete parallelization of H.264, which is the most advanced video coding standard, was found to be difficult due to the complexity of the standard. In this paper a parallel implementation of a complete H.264 decoder is presented. Our parallelization strategy exploits function-level as well as data-level parallelism. Function-level parallelism is used to pipeline the H.264 decoding stages. Data-level parallelism is exploited within the two most time consuming stages, the entropy decoding stage and the macroblock decoding stage. The parallelization strategy has been implemented and optimized on three platforms with very different memory architectures, namely an 8-core SMP, a 64-core cc-NUMA, and an 18-core Cell platform. Evaluations have been performed using 4kx2k QHD sequences. On the SMP platform a maximum speedup of 4.5x is achieved. The SMP-implementation is reasonably performance portable as it achieves a speedup of 26.6x on the cc-NUMA system. However, to obtain the highest performance (speedup of 33.4x and throughput of 200 QHD frames per second), several cc-NUMA specific optimizations are necessary such as optimizing the page placement and statically assigning threads to cores. Finally, on the Cell platform a near ideal speedup of 16.5x is achieved by completely hiding the communication latency. | en |
| dc.description.sponsorship | EC/FP7/248647/EU/ENabling technologies for a programmable many-CORE/ENCORE | en |
| dc.identifier.isbn | 978-1-4503-0102-2 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/7019 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-6340 | |
| dc.language.iso | en | |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | |
| dc.subject.other | 4k x 2k | en |
| dc.subject.other | cell | en |
| dc.subject.other | decoding | en |
| dc.subject.other | h.264 | en |
| dc.subject.other | numa | en |
| dc.subject.other | parallel | en |
| dc.subject.other | smp | en |
| dc.title | A QHD-capable parallel H.264 decoder | en |
| dc.type | Conference Object | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1145/1995896.1995945 | |
| dcterms.bibliographicCitation.originalpublishername | Association for Computing Machinery (ACM) | en |
| dcterms.bibliographicCitation.originalpublisherplace | New York, NY | en |
| dcterms.bibliographicCitation.pageend | 326 | |
| dcterms.bibliographicCitation.pagestart | 317 | |
| dcterms.bibliographicCitation.proceedingstitle | Proceedings of the International Conference on Supercomputing | en |
| tub.accessrights.dnb | domain | |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |
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