Lucas, JanLal, SohanJuurlink, Ben2018-06-012018-06-012018978-3-9819263-1-6978-3-9819263-0-9https://depositonce.tu-berlin.de/handle/11303/7900http://dx.doi.org/10.14279/depositonce-7061GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area.en004 Datenverarbeitung; Informatikdata bus inversionDDR4GDDR5power consumptiontermination powerConference Object1558-1101