Alawneh, TareqChi, Chi ChingElhossini, AhmedJuurlink, Ben2018-07-122018-07-1220150177-0454https://depositonce.tu-berlin.de/handle/11303/8014http://dx.doi.org/10.14279/depositonce-7177Recent research results show that there is a high degree of code sharing between cores in multi-core architectures. In this paper we propose a proximity scheme for the instruction caches, a scheme in which the shared code blocks among the neighbouring L2 caches in tiled multi-core architectures are exploited to reduce the average cache miss penalty and the on-chip network traffic. We evaluate the proposed proximity scheme for instruction caches using a full-system simulator running an n-core tiled CMP. The experimental results reveal a significant execution time improvement of up to 91.4% for microbenchmarks whose instruction footprint does not fit in the private L2 cache. For real applications from the PARSEC benchmarks suite, the proposed scheme results in speedups of up to 8%.en004 Datenverarbeitung; Informatikchip multiprocessormulti-core architecturescachebenchmarkCMPArticle