Göbel, MatthiasElhossini, AhmedJuurlink, Ben2018-06-072018-06-072017978-1-5386-2146-2https://depositonce.tu-berlin.de/handle/11303/7918http://dx.doi.org/10.14279/depositonce-7079The trend of using heterogeneous computing and HW/SW-Codesign approaches allows increasing performance significantly while reducing power consumption. One of the main challenges when combining multiple processing devices is the communication, as an inefficient communication configuration can pose a bottleneck to the overall system performance. To address this problem, we present a methodology that assists the designer in making good design decisions for systems using shared DDR memory for communication. Our methodology analyzes a software implementation of the application and subsequently predicts the memory accesses of a functionally equivalent hardware implementation of the selected function. We furthermore propose an IP core that can perform these predicted memory accesses to estimate the achievable memory bandwidth between a functionally equivalent hardware implementation and shared memory. The resulting achievable memory bandwidth estimations differ by less than 2% from the actual achievable memory bandwidth of a functionally equivalent hardware implementation, demonstrating the feasibility of the presented methodology.en004 Datenverarbeitung; Informatikmemory accessFPGA-SoCmemory bandwidthHW/SW-Codesignmemory estimationmemory predictionConference Object