A Quantitative Analysis of the Memory Architecture of FPGA-SoCs
| dc.contributor.author | Göbel, Matthias | |
| dc.contributor.author | Elhossini, Ahmed | |
| dc.contributor.author | Chi, Chi Ching | |
| dc.contributor.author | Álvarez-Mesa, Mauricio | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2018-06-08T12:18:16Z | |
| dc.date.available | 2018-06-08T12:18:16Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | In recent years, so called FPGA-SoCs have been introduced by Intel (formerly Altera) and Xilinx. These devices combine multi-core processors with programmable logic. This paper analyzes the various memory and communication interconnects found in actual devices, particularly the Zynq-7020 and Zynq-7045 from Xilinx and the Cyclone V SE SoC from Intel. Issues such as different access patterns, cache coherence and full-duplex communication are analyzed, for both generic accesses as well as for a real workload from the field of video coding. Furthermore, the paper shows that by carefully choosing the memory interconnect networks as well as the software interface, high-speed memory access can be achieved for various scenarios. | en |
| dc.identifier.eissn | 1611-3349 | |
| dc.identifier.isbn | 978-3-319-56257-5 | |
| dc.identifier.isbn | 978-3-319-56258-2 | |
| dc.identifier.issn | 0302-9743 | |
| dc.identifier.uri | https://depositonce.tu-berlin.de/handle/11303/7928 | |
| dc.identifier.uri | http://dx.doi.org/10.14279/depositonce-7089 | |
| dc.language.iso | en | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject.ddc | 004 Datenverarbeitung; Informatik | de |
| dc.subject.other | programmable logic | en |
| dc.subject.other | memory | en |
| dc.subject.other | video coding | en |
| dc.subject.other | bandwidth | en |
| dc.subject.other | FPGA | en |
| dc.title | A Quantitative Analysis of the Memory Architecture of FPGA-SoCs | en |
| dc.type | Conference Object | en |
| dc.type.version | acceptedVersion | en |
| dcterms.bibliographicCitation.doi | 10.1007/978-3-319-56258-2_21 | en |
| dcterms.bibliographicCitation.originalpublishername | Springer | en |
| dcterms.bibliographicCitation.originalpublisherplace | Cham | en |
| dcterms.bibliographicCitation.pageend | 252 | en |
| dcterms.bibliographicCitation.pagestart | 241 | en |
| dcterms.bibliographicCitation.proceedingstitle | Applied reconfigurable computing : 13th International Symposium, ARC 2017, Delft, the Netherlands, April 3-7, 2017, Proceedings | en |
| tub.accessrights.dnb | free | en |
| tub.affiliation | Fak. 4 Elektrotechnik und Informatik::Inst. Technische Informatik und Mikroelektronik::FG Architektur eingebetteter Systeme | de |
| tub.affiliation.faculty | Fak. 4 Elektrotechnik und Informatik | de |
| tub.affiliation.group | FG Architektur eingebetteter Systeme | de |
| tub.affiliation.institute | Inst. Technische Informatik und Mikroelektronik | de |
| tub.publisher.universityorinstitution | Technische Universität Berlin | en |
| tub.series.issuenumber | 10216 | en |
| tub.series.name | Lecture Notes in Computer Science | en |