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🆕 Date Issued:
2010
🗄 In DepositOnce:2018-06-01
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The SARC Architecture

Ramirez, Alex; Cabarcas, Felipe; Juurlink, Ben; Álvarez-Mesa, Mauricio; Sanchez, Friman; Azevedo, Arnaldo; Meenderinck, Cor; Ciobanu, Cătălin; Isaza, Sebastian; Gaydadjiev, Georgi

The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.
programming modelmulticoreheterogeneous architectureaccelerator
Published in: IEEE micro : chips, systems, software, and applications, 10.1109/MM.2010.79, IEEE
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